1. Field of Invention
The present invention relates generally to computer data retrieval systems. More particularly the present invention relates to phase-locked-loops (PLL) for adjusting phase differences between transmitting and receiving mechanisms. Specifically, the present invention relates to a computer based system and method for receiving data from memory and adjusting for mechanical speed variations of the external and/or internal data transferring mechanisms.
2. Related Art
Over the past several decades, society has placed an increasingly larger demand on the speed at which it expects computers to operate. A tremendous amount of effort and resources have been spent to satisfy this demand. As a result, the data transfer rate in computers has increased significantly. This increase in speed causes new problems. As data is read at a greater rate the allowable tolerance in the data window (clock cell) decreases.
In practice, data streams contain bit jitter or imperfect bit spacing due to a variety of causes, including: varying code sequences, head roll, variations in disk drive speed, and magnetic crowding effects. As a result, data phase errors must be quickly reduced in order to keep data transfer accurate.
The difficulty involved in synchronizing two or more devices is a concern which has been addressed frequently. In general, when each device has its own clock, the problem is that these clocks must be synchronized in order to allow meaningful interaction between the devices. When only clocks are involved the solution is fairly straightforward. A conventional phase-locked-loop is used to compare one clock to another. If the clocks are out of phase a phase detector sends an appropriate current to an RC filter. This RC filter generates a voltage that directs a voltage controlled oscillator to modify the clock rate. The two clocks are quickly "locked" to each other and meaningful interaction can occur.
When data is being transmitted, however, the problem of synchronizing the devices becomes more complicated. When receiving a data signal a phase detector is concerned about two items: first, is there data in the data window; and, second, if there is data, by how much is the data out of phase with respect to the receiving device's data window. The data window is the time allotted for each data bit to be read by the receiving device's clock. The data window is also known as a clock cell. A phase detector that must predetermine whether there is data in the next data window is more complicated in structure than one that can discern this information using other methods.
Ideally a data transition, which is the leading edge of a data bit, occurs at the center of a data window. If a data transition occurs early in the data window then the phase detector knows that data is present and a signal indicating the phase shift of the data transition can begin immediately. However, if a data transition does not appear by the center of the data window then a problem occurs. In order to adjust for a data-late transition the phase detector must begin its phase error signal at the center of the data window. However at this point the phase detector does not know if there is a data transition in this data window. Therefore the signal cannot be generated without using complicated logic.
Another problem facing phase-locked loops is that a modification in the voltage controlled oscillator only affects future data. Adjusting for random or one-time only errors is counterproductive. This is because such adjustments to the clock, and therefore the data window, will not generally ensure that future data transitions are at the center of the data window. Magnetic crowding is an example of the type of data phase error that is random. Variations in disk drive speed, e.g., because of slippage, is a condition which will cause data phase errors to appear consistently in future data windows.
Generally, phase-locked loops are used to synchronize pulses. A phase-locked loop contains a phase detector, amplifier, and a voltage-controlled oscillator (VCO). If two clocks are involved, the phase detector compares two frequencies, an input frequency and a voltage controlled oscillator frequency. The phase detector generates an output that is a measure of their phase difference. This output, or phase-error signal, is then filtered and amplified before reaching the voltage controlled oscillator. The voltage controlled oscillator's frequency is altered in the direction of the incoming frequency. The voltage controlled oscillator should quickly "lock" onto the incoming frequency.
The conventional phase detectors used in phase-locked loops are sensitive to the relative timing of edges between the input signal frequency and the voltage controlled oscillator. The internal circuitry generates either lead or lag output pulses. Which pulse is generated depends on when the transitions of the input signal occur with respect to the voltage controlled oscillator frequency. The width of these pulses is equal to the time between the edges of the voltage controlled oscillator frequency, i.e., the time between the center of the data window, and the signal transition. These pulses are input into a charge pump which generates either a sink or source current depending on whether the signal is late or early, see generally IBM Technical Disclosure Bulletin, Vol. 27, No. 9, (February 1985), incorporated herein by reference.
Some current data phase-locked loops analyze an incoming data stream one data window at a time. A data transition is sent to a data phase detector. A signal is then output corresponding to the phase error of the data transition. The phase error is the phase difference between the time of actual data transition and the center of the data window. Recognizing that the voltage controlled oscillator should modify its signal based on an average of several data bits, the current technology uses filters to store a charge until the next data window. This technique does not provide the opportunity to use a greater sampling of data when generating the error signal. Therefore its effectiveness is limited.
Other conventional data phase-locked loops simply adjust the voltage controlled oscillator as it encounters each data bit. The problem with this technique is that all errors, consistent and random, are treated equally and affect the voltage controlled oscillator equally. See, e.g., IBM Technical Disclosure Bulletin, Vol. 25, No. 3B (August 1982), incorporated herein by reference.
Since voltage controlled oscillators make corrections affecting only future data, the random errors should not cause the voltage controlled oscillator to alter the data window. Instead, only consistently occurring errors should affect the voltage controlled oscillator.